mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 03:32:29 +00:00 
			
		
		
		
	Otherwise the `AST_PRIMITIVE` simplifies to the corresponding function and is no longer caught by the check for `AST_PRIMITIVE`s, raising an assertion error instead of an input error. Add bug4785.ys to tests/verilog to demonstrate.
		
			
				
	
	
		
			9 lines
		
	
	
	
		
			215 B
		
	
	
	
		
			Text
		
	
	
	
	
	
			
		
		
	
	
			9 lines
		
	
	
	
		
			215 B
		
	
	
	
		
			Text
		
	
	
	
	
	
| logger -expect error "Cell arrays of primitives are currently not supported" 1
 | |
| read_verilog <<EOT
 | |
| module test(in1, in2, out1);
 | |
|   input in1, in2;
 | |
|   output out1;
 | |
| 
 | |
|   nand  #2 t_nand[0:7](out1, in1, in2);
 | |
| endmodule
 | |
| EOT
 |