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51 lines
1.7 KiB
Verilog
51 lines
1.7 KiB
Verilog
module \$_DFFE_PN0P_ (input D, C, R, E, output Q);
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SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
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endmodule
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module \$_DFFE_PN1P_ (input D, C, R, E, output Q);
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SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
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endmodule
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module \$_SDFFCE_PN0P_ (input D, C, R, E, output Q);
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SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(1'b1), .ADn(1'b0), .SLn(R), .SD(1'b0), .LAT(1'b0), .Q(Q));
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endmodule
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module \$_SDFFCE_PN1P_ (input D, C, R, E, output Q);
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SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(1'b1), .ADn(1'b0), .SLn(R), .SD(1'b1), .LAT(1'b0), .Q(Q));
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endmodule
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module \$_DLATCH_PN0_ (input D, R, E, output Q);
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SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
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endmodule
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module \$_DLATCH_PN1_ (input D, R, E, output Q);
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SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
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endmodule
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`ifndef NO_LUT
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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(* force_downto *)
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]));
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end else
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if (WIDTH == 2) begin
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CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]));
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end else
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if (WIDTH == 3) begin
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CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]));
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end else
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if (WIDTH == 4) begin
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CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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`endif
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