Clifford Wolf 57fc8dd582 Add "synth_ice40 -json" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2018-06-13 13:35:10 +02:00
..
tests
.gitignore
arith_map.v
brams.txt
brams_init.py
brams_map.v
cells_map.v	Improving vpr output support.	2018-04-18 16:55:12 -07:00
cells_sim.v	Avoid mixing module port declaration styles in ice40 cells_sim.v	2018-05-17 13:54:43 +02:00
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc	Fix ice40_opt for cases where a port is connected to a signal with width != 1	2018-06-11 18:12:42 +02:00
latches_map.v
Makefile.inc
synth_ice40.cc	Add "synth_ice40 -json"	2018-06-13 13:35:10 +02:00