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Code Activity
yosys/backends/verilog
History
Emil J. Tywoniak 5f437ab076 write_verilog: write out src twines as src attributes
2026-07-20 15:01:30 +02:00
..
CMakeLists.txt Migrate build system to CMake 2026-06-03 08:58:10 +00:00
verilog_backend.cc write_verilog: write out src twines as src attributes 2026-07-20 15:01:30 +02:00
verilog_backend.h verilog backend: runtime optimization for keyword pool 2026-05-29 17:53:31 +00:00