mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-10 13:10:51 +00:00
3 lines
74 B
Verilog
3 lines
74 B
Verilog
module TECH_AND5(input [4:0] in, output out);
|
|
assign out = ∈
|
|
endmodule
|