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Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present.
17 lines
492 B
Plaintext
17 lines
492 B
Plaintext
read_verilog latches.v
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design -save read
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proc
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async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
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flatten
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synth_anlogic
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equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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design -load read
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synth_anlogic
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cd top
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select -assert-count 2 t:AL_MAP_LUT3
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select -assert-count 1 t:AL_MAP_LUT5
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select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT5 %% t:* %D
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