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27377c4663
Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present.
59 lines
742 B
Verilog
59 lines
742 B
Verilog
module latchp
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( input d, clk, en, output reg q );
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always @*
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if ( en )
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q <= d;
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endmodule
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module latchn
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( input d, clk, en, output reg q );
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always @*
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if ( !en )
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q <= d;
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endmodule
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module latchsr
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( input d, clk, en, clr, pre, output reg q );
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always @*
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if ( clr )
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q <= 1'b0;
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else if ( pre )
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q <= 1'b1;
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else if ( en )
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q <= d;
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endmodule
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module top (
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input clk,
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input clr,
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input pre,
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input a,
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output b,b1,b2
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);
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latchp u_latchp (
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.en (clk ),
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.d (a ),
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.q (b )
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);
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latchn u_latchn (
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.en (clk ),
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.d (a ),
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.q (b1 )
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);
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latchsr u_latchsr (
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.en (clk ),
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.clr (clr),
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.pre (pre),
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.d (a ),
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.q (b2 )
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);
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endmodule
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