Eddie Hung 76e0cc8276 ecp5: cleanup unused +/ecp5/abc9_model.v		2020-05-23 08:17:40 -07:00
..
tests
.gitignore
arith_map.v	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
brams.txt	ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.	2020-02-06 16:52:51 +00:00
brams_connect.py
brams_init.py
brams_map.v	remove unused parameters	2020-03-06 16:45:36 +01:00
cells_bb.v	ecp5: Add missing SERDES parameters	2020-05-12 21:12:26 +01:00
cells_ff.vh	Fix bitwidth mismatch; suppresses iverilog warning	2019-12-11 13:02:07 -08:00
cells_io.vh
cells_map.v	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
cells_sim.v	ecp5: TRELLIS_FF bypass path only in async mode	2020-05-14 10:33:56 -07:00
dsp_map.v	ecp5: Force SIGNED ports to be 1 bit	2020-04-16 16:38:19 +01:00
ecp5_ffinit.cc	Cleanup use of hard-coded default parameters in light of #1945	2020-04-22 12:02:30 -07:00
ecp5_gsr.cc	ecp5: ecp5_gsr to skip cells that don't have GSR parameter again	2020-04-22 17:53:08 -07:00
latches_map.v
lutrams.txt	ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.	2020-02-06 16:52:51 +00:00
lutrams_map.v
Makefile.inc	ecp5: cleanup unused +/ecp5/abc9_model.v	2020-05-23 08:17:40 -07:00
synth_ecp5.cc	ecp5: cleanup unused +/ecp5/abc9_model.v	2020-05-23 08:17:40 -07:00