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yosys/techlibs
2026-07-24 11:13:22 +02:00
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achronix End of file fix 2026-06-23 07:23:41 +02:00
analogdevices Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
anlogic Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
common flowmap: remove 2026-07-22 13:50:33 +01:00
coolrunner2 Migrate build system to CMake 2026-06-03 08:58:10 +00:00
easic Migrate build system to CMake 2026-06-03 08:58:10 +00:00
efinix check make always_latch exempt. 2026-07-24 11:13:22 +02:00
fabulous check make always_latch exempt. 2026-07-24 11:13:22 +02:00
gatemate Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
gowin Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
greenpak4 Migrate build system to CMake 2026-06-03 08:58:10 +00:00
ice40 check make always_latch exempt. 2026-07-24 11:13:22 +02:00
intel End of file fix 2026-06-23 07:23:41 +02:00
intel_alm Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
lattice check make always_latch exempt. 2026-07-24 11:13:22 +02:00
microchip Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
nanoxplore check make always_latch exempt. 2026-07-24 11:13:22 +02:00
quicklogic check make always_latch exempt. 2026-07-24 11:13:22 +02:00
sf2 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
xilinx xilinx_srl: keep the clock enable on FDRE shift registers 2026-07-20 23:59:40 -07:00
CMakeLists.txt Migrate build system to CMake 2026-06-03 08:58:10 +00:00
fix_mod.py Remove trailing whitespaces 2026-06-23 07:24:59 +02:00