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https://github.com/YosysHQ/yosys
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3187275184
This ensure the build flags used elsewhere are included also during testing. Patch based on change from Daniel Gröber via Debian. See also issue #5805.
242 lines
7.2 KiB
Bash
Executable file
242 lines
7.2 KiB
Bash
Executable file
#!/usr/bin/env bash
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libs=()
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genvcd=false
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use_xsim=false
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use_modelsim=false
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verbose=false
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keeprunning=false
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makejmode=false
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frontend="verilog -noblackbox"
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backend_opts="-noattr -noexpr -siminit"
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autotb_opts=""
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include_opts=""
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xinclude_opts=""
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minclude_opts=""
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scriptfiles=""
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scriptopt=""
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toolsdir="$(cd "$(dirname "$0")"; pwd)"
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warn_iverilog_git=false
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# The following are used in verilog to firrtl regression tests.
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# Typically these will be passed as environment variables:
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#EXTRA_FLAGS="--firrtl2verilog 'java -cp /.../firrtl/utils/bin/firrtl.jar firrtl.Driver'"
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# The tests are skipped if firrtl2verilog is the empty string (the default).
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firrtl2verilog=""
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xfirrtl="../xfirrtl"
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abcprog="$toolsdir/../../yosys-abc"
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if [ ! -f "$toolsdir/cmp_tbdata" -o "$toolsdir/cmp_tbdata.c" -nt "$toolsdir/cmp_tbdata" ]; then
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( set -ex; ${CXX:-g++} -Wall ${CPPFLAGS} ${CXXFLAGS:-} -o "$toolsdir/cmp_tbdata" "$toolsdir/cmp_tbdata.c"; ) || exit 1
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fi
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while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do
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case "$opt" in
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x)
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use_xsim=true ;;
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m)
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use_modelsim=true ;;
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G)
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warn_iverilog_git=true ;;
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l)
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libs+=("$(cd "$(dirname "$OPTARG")"; pwd)/$(basename "$OPTARG")");;
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w)
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genvcd=true ;;
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k)
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keeprunning=true ;;
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j)
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makejmode=true ;;
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v)
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verbose=true ;;
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r)
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backend_opts="$backend_opts -norename" ;;
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e)
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backend_opts="$( echo " $backend_opts " | sed 's, -noexpr , ,; s,^ ,,; s, $,,;'; )" ;;
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f)
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frontend="$OPTARG" ;;
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s)
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[[ "$OPTARG" == /* ]] || OPTARG="$PWD/$OPTARG"
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scriptfiles="$scriptfiles $OPTARG" ;;
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p)
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scriptopt="$OPTARG" ;;
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n)
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autotb_opts="$autotb_opts -n $OPTARG" ;;
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S)
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autotb_opts="$autotb_opts -seed $OPTARG" ;;
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I)
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include_opts="$include_opts -I $OPTARG"
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xinclude_opts="$xinclude_opts -i $OPTARG"
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minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
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A)
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abcprog="$OPTARG" ;;
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-)
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case "${OPTARG}" in
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xfirrtl)
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xfirrtl="${!OPTIND}"
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OPTIND=$(( $OPTIND + 1 ))
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;;
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firrtl2verilog)
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firrtl2verilog="${!OPTIND}"
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OPTIND=$(( $OPTIND + 1 ))
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;;
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*)
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if [ "$OPTERR" == 1 ] && [ "${optspec:0:1}" != ":" ]; then
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echo "Unknown option --${OPTARG}" >&2
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fi
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;;
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esac;;
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*)
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echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
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exit 1
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esac
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done
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compile_and_run() {
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exe="$1"; output="$2"; shift 2
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if [ "${2##*.}" == "sv" ]; then
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language_gen="-g2012"
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else
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language_gen="-g2005"
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fi
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if $use_modelsim; then
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altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
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/opt/altera/$altver/modelsim_ase/bin/vlib work
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/opt/altera/$altver/modelsim_ase/bin/vlog $minclude_opts +define+outfile=\"$output\" "$@"
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/opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench
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elif $use_xsim; then
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xilver=$( ls -v /opt/Xilinx/Vivado/ | grep '^[0-9]' | tail -n1; )
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/opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@"
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/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench
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else
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iverilog $language_gen $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
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vvp -n "$exe"
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fi
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}
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shift $((OPTIND - 1))
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for fn
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do
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bn=${fn%.*}
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ext=${fn##*.}
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if [[ "$ext" != "v" ]] && [[ "$ext" != "sv" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
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echo "Invalid argument: $fn" >&2
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exit 1
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fi
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[[ "$bn" == *_tb ]] && continue
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if $makejmode; then
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status_prefix="Test: $bn "
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else
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status_prefix=""
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echo -n "Test: $bn "
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fi
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if [ "$ext" == sv ]; then
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frontend="$frontend -sv"
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fi
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rm -f ${bn}.{err,log,skip}
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mkdir -p ${bn}.out
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rm -rf ${bn}.out/*
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body() {
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cd ${bn}.out
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fn=$(basename $fn)
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bn=$(basename $bn)
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refext=v
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rm -f ${bn}_ref.fir
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if [[ "$ext" == "v" ]]; then
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grep -Ev '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
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elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then
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$abcprog -c "read_aiger ../${fn}; write ${bn}_ref.${refext}"
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else
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refext=$ext
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cp ../${fn} ${bn}_ref.${refext}
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fi
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if [ ! -f ../${bn}_tb.v ]; then
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"$toolsdir"/../../yosys -f "$frontend $include_opts -D_AUTOTB" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext}
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else
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cp ../${bn}_tb.v ${bn}_tb.v
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fi
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if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
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touch ${bn}.iverilog
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compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} "${libs[@]}" \
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"$toolsdir"/../../techlibs/common/simlib.v \
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"$toolsdir"/../../techlibs/common/simcells.v
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rm ${bn}.iverilog
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if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
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test_count=0
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test_passes() {
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"$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
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touch ${bn}.iverilog
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compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
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${bn}_tb.v ${bn}_syn${test_count}.v "${libs[@]}" \
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"$toolsdir"/../../techlibs/common/simlib.v \
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"$toolsdir"/../../techlibs/common/simcells.v
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if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
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"$toolsdir/cmp_tbdata" ${bn}_out_ref ${bn}_out_syn${test_count}
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rm ${bn}.iverilog
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test_count=$(( test_count + 1 ))
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}
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if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP ${bn}_ref.${refext}; then
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touch ../${bn}.skip
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return
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fi
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if [ -n "$scriptfiles" ]; then
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test_passes -f "$frontend $include_opts" ${bn}_ref.${refext} $scriptfiles
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elif [ -n "$scriptopt" ]; then
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test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.${refext}
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elif [ "$frontend" = "verific" ]; then
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test_passes -p "verific -vlog2k ${bn}_ref.${refext}; verific -import -all; opt; memory;;"
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elif [ "$frontend" = "verific_gates" ]; then
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test_passes -p "verific -vlog2k ${bn}_ref.${refext}; verific -import -gates -all; opt; memory;;"
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else
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test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine" ${bn}_ref.${refext}
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test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext}
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if [ -n "$firrtl2verilog" ]; then
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if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
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"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
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$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
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test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine" ${bn}_ref.fir.v
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fi
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fi
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fi
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touch ../${bn}.log
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}
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if $verbose; then
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echo ".."
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echo "Output written to console." > ${bn}.err
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( set -ex; body; )
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else
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( set -ex; body; ) > ${bn}.err 2>&1
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fi
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did_firrtl=""
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if [ -f ${bn}.out/${bn}_ref.fir ]; then
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did_firrtl="+FIRRTL "
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fi
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if [ -f ${bn}.log ]; then
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mv ${bn}.err ${bn}.log
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echo "${status_prefix}${did_firrtl}-> ok"
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elif [ -f ${bn}.skip ]; then
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mv ${bn}.err ${bn}.skip
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echo "${status_prefix}-> skip"
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else
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echo "${status_prefix}${did_firrtl}-> ERROR!"
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if $warn_iverilog_git; then
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if [ -f ${bn}.out/${bn}.iverilog ]; then
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echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
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fi
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fi
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$keeprunning || exit 1
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fi
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done
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exit 0
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