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Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
13 lines
279 B
Text
13 lines
279 B
Text
read_verilog ../common/blockram.v
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hierarchy -top sync_ram_sp
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proc
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memory -nomap
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equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
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memory
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opt -full
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design -load postopt
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cd sync_ram_sp
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select -assert-count 1 t:EG_PHY_BRAM
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select -assert-none t:EG_PHY_BRAM %% t:* %D
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