mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-11 03:33:36 +00:00
13 lines
290 B
Verilog
13 lines
290 B
Verilog
(* abc_box_id = 1 *)
|
|
module SB_CARRY (output CO, input CI, I0, I1);
|
|
assign CO = (I0 && I1) || ((I0 || I1) && CI);
|
|
endmodule
|
|
|
|
(* abc_box_id = 2 *)
|
|
module SB_LUT4 (output O, input I0, I1, I2, I3);
|
|
parameter [15:0] LUT_INIT = 0;
|
|
// Indicate this is a black-box
|
|
assign O = 1'b0;
|
|
endmodule
|
|
|