mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-27 09:49:25 +00:00
Code Activity
yosys/backends/firrtl
History
Adam Izraelevitz 794cec0016 More progress on Firrtl backend. 
Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a
simple rocket-chip design.
2017-02-13 11:17:53 -08:00
..
.gitignore
firrtl.cc More progress on Firrtl backend. 2017-02-13 11:17:53 -08:00
Makefile.inc
test.sh More progress on Firrtl backend. 2017-02-13 11:17:53 -08:00
test.v More progress on Firrtl backend. 2017-02-13 11:17:53 -08:00