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27 lines
469 B
Verilog
27 lines
469 B
Verilog
module constmuldivmod(input [7:0] A, input [2:0] mode, output reg [7:0] Y);
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always @* begin
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case (mode)
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0: Y = A / 8'd0;
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1: Y = A % 8'd0;
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2: Y = A * 8'd0;
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3: Y = A / 8'd1;
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4: Y = A % 8'd1;
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5: Y = A * 8'd1;
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6: Y = A / 8'd2;
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7: Y = A % 8'd2;
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8: Y = A * 8'd2;
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9: Y = A / 8'd4;
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10: Y = A % 8'd4;
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11: Y = A * 8'd4;
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12: Y = A / 8'd8;
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13: Y = A % 8'd8;
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14: Y = A * 8'd8;
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default: Y = 8'd16 * A;
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endcase
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end
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endmodule
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