mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity
yosys/techlibs/intel
History
Marcelina Kościelnicka 88e7f90663 Update dff2dffe, dff2dffs, zinit to new FF types.
2020-06-23 18:24:53 +02:00
..
arria10gx Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
common intel: Map M9K BRAM only on families that have it 2019-07-23 18:11:11 +01:00
cyclone10lp Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
cycloneiv Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
cycloneive Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
cyclonev Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
max10 Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
Makefile.inc synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
synth_intel.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00