Emil J. Tywoniak 6240aec433 test: restore verific handling, nicer naming		2024-12-13 10:24:47 +01:00
..
.gitignore
add_sub.ys
adffs.ys
counter.ys
dffs.ys
div.ys	quicklogic: Relax the LUT number test	2024-10-07 15:27:03 +02:00
dsp.ys	tests: Run async2sync before sat and/or sim to handle $check cells	2024-02-01 16:14:11 +01:00
fsm.ys
latches.ys
logic.ys
mem_gen.py	tests: Run async2sync before sat and/or sim to handle $check cells	2024-02-01 16:14:11 +01:00
mem_tb.v
meminit.v	quicklogic: Test TDP36K inference with initial data	2023-12-04 15:52:03 +01:00
meminit.ys	tests: Run async2sync before sat and/or sim to handle $check cells	2024-02-01 16:14:11 +01:00
mux.ys
run-test.sh	test: restore verific handling, nicer naming	2024-12-13 10:24:47 +01:00