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73 lines
2.7 KiB
Text
73 lines
2.7 KiB
Text
read_verilog <<EOT
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module top (
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input CLK, PIN_1, PIN_2, PIN_3, PIN_4, PIN_5,
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PIN_6, PIN_7, PIN_8, PIN_9, PIN_10, PIN_11, PIN_12, PIN_13, PIN_25,
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output USBPU, PIN_14, PIN_15, PIN_16, PIN_17, PIN_18,
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PIN_19,
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);
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assign USBPU = 0;
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wire[5:0] parOut;
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wire[5:0] chrg;
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assign PIN_14 = parOut[0];
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assign PIN_15 = parOut[1];
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assign PIN_16 = parOut[2];
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assign PIN_17 = parOut[3];
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assign PIN_18 = parOut[4];
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assign PIN_19 = parOut[5];
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assign chrg[0] = PIN_3;
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assign chrg[1] = PIN_4;
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assign chrg[2] = PIN_5;
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assign chrg[3] = PIN_6;
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assign chrg[4] = PIN_7;
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assign chrg[5] = PIN_8;
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SSCounter6o sc6(PIN_1, CLK, PIN_2, PIN_9, chrg, parOut);
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endmodule
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module SSCounter6 (input wire rst, clk, adv, jmp, input wire [5:0] in, output reg[5:0] out);
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always @(posedge clk, posedge rst)
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if (rst) out <= 0;
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else if (adv || jmp) out <= jmp ? in : out + 1;
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endmodule
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// Optimized 6 bit counter, it should takes 7 cells.
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/* b[5:1] /* b[0]
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1010101010101010 in 1010101010101010 in
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1100110011001100 jmp 1100110011001100 jmp
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1111000011110000 loop 1111000011110000 loop
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1111111100000000 carry 1111111100000000 -
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---------------------- ----------------------
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1000101110111000 out 1000101110001011 out
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8 B B 8 8 B 8 B
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*/
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module SSCounter6o (input wire rst, clk, adv, jmp, input wire [5:0] in, output wire[5:0] out);
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wire[4:0] co;
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wire[5:0] lo;
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wire ien;
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SB_LUT4 #(.LUT_INIT(16'hFFF0)) lien (ien, 0, 0, adv, jmp);
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SB_CARRY c0 (co[0], jmp, out[0], 1),
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c1 (co[1], jmp, out[1], co[0]),
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c2 (co[2], jmp, out[2], co[1]),
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c3 (co[3], jmp, out[3], co[2]),
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c4 (co[4], jmp, out[4], co[3]);
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SB_DFFER d0 (out[0], clk, ien, rst, lo[0]),
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d1 (out[1], clk, ien, rst, lo[1]),
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d2 (out[2], clk, ien, rst, lo[2]),
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d3 (out[3], clk, ien, rst, lo[3]),
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d4 (out[4], clk, ien, rst, lo[4]),
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d5 (out[5], clk, ien, rst, lo[5]);
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SB_LUT4 #(.LUT_INIT(16'h8B8B)) l0 (lo[0], in[0], jmp, out[0], 0);
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SB_LUT4 #(.LUT_INIT(16'h8BB8)) l1 (lo[1], in[1], jmp, out[1], co[0]);
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SB_LUT4 #(.LUT_INIT(16'h8BB8)) l2 (lo[2], in[2], jmp, out[2], co[1]);
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SB_LUT4 #(.LUT_INIT(16'h8BB8)) l3 (lo[3], in[3], jmp, out[3], co[2]);
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SB_LUT4 #(.LUT_INIT(16'h8BB8)) l4 (lo[4], in[4], jmp, out[4], co[3]);
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SB_LUT4 #(.LUT_INIT(16'h8BB8)) l5 (lo[5], in[5], jmp, out[5], co[4]);
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endmodule
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EOT
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read_verilog -lib +/ice40/cells_sim.v
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hierarchy -top top
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flatten
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equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40
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