mirror of
https://github.com/YosysHQ/yosys
synced 2026-03-23 21:09:14 +00:00
68 lines
2 KiB
Python
68 lines
2 KiB
Python
#!/usr/bin/env python3
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import glob
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import os
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yosys = "../../yosys"
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default_abc = "../../yosys-abc"
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aags = sorted(glob.glob("*.aag"))
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yss = sorted(glob.glob("*.ys"))
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print("ABC ?= " + default_abc)
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print("YOSYS ?= " + yosys)
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print()
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def base(fn):
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return os.path.splitext(fn)[0]
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# NB: *.aag and *.aig must contain a symbol table naming the primary
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# inputs and outputs, otherwise ABC and Yosys will name them
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# arbitrarily (and inconsistently with each other).
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# Since ABC cannot read *.aag, read the *.aig instead
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# (which would have been created by the reference aig2aig utility,
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# available from http://fmv.jku.at/aiger/)
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for aag in aags:
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b = base(aag)
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print(f"all: {aag}")
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print(f".PHONY: {aag}")
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print(f"{aag}:")
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print(f"\t@echo Checking {aag}.")
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print(f"\t@$(ABC) -q \"read -c {b}.aig; write {b}_ref.v\" >/dev/null 2>&1")
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print("\t@$(YOSYS) -qp \"\\")
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print(f"\tread_verilog {b}_ref.v; \\")
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print("\tprep; \\")
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print("\tdesign -stash gold; \\")
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print(f"\tread_aiger -clk_name clock {aag}; \\")
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print("\tprep; \\")
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print("\tdesign -stash gate; \\")
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print("\tdesign -import gold -as gold; \\")
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print("\tdesign -import gate -as gate; \\")
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print("\tmiter -equiv -flatten -make_assert -make_outputs gold gate miter; \\")
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print("\tsat -verify -prove-asserts -show-ports -seq 16 miter; \\")
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print(f"\t\" -l {aag}.log >/dev/null 2>&1")
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print()
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# ---- Yosys script tests ----
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for ys in yss:
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b = base(ys)
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print(f"all: {ys}")
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print(f".PHONY: {ys}")
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print(f"{ys}: ")
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print(f"\t@echo Running {ys}.")
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print(f"\t@$(YOSYS) -ql {b}.log {ys} >/dev/null 2>&1")
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print()
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# ---- aigmap test ----
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print(f"all: aigmap")
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print(f".PHONY: aigmap")
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print("aigmap:")
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print("\t@echo Running aigmap.")
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print("\t@rm -rf gate; mkdir gate")
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print('\t@$(YOSYS) --no-version -p "test_cell -aigmap -w gate/ -n 1 -s 1 all" >/dev/null 2>&1')
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print("\t@set -o pipefail; diff --brief gold gate | tee aigmap.err")
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print("\t@rm -f aigmap.err")
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print()
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