yosys/tests/simple/memwr_port_connection.sv at 2f609a313643b2462ab692a4295e6f73f96f35db - mirrors/yosys - Libre-Chip.org

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Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections

- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change

2021-10-25 18:25:50 -07:00

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Systemverilog

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 module producer(
     output logic [3:0] out
 );
     assign out = 4'hA;
 endmodule
 module top(
     output logic [3:0] out
 );
     logic [3:0] v[0:0];
     producer p(v[0]);
     assign out = v[0];
 endmodule