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https://github.com/YosysHQ/yosys
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a55bf6375b
The already-existing special case for conditionals on clock has been remade as follows: - now triggered for the last remaining edge trigger after all others have been converted to async reset, not just when there is only one sync rule in the first place - does not require all contained assignments to be constant, as opposed to a reset conditional — merely const-folds the condition In addition, the code has been refactored a bit; as a bonus, the priority order of async resets found is now preserved in resulting sync rule ordering (though this is not yet respected by proc_dff). Fixes #2656.
31 lines
615 B
Text
31 lines
615 B
Text
read_verilog <<EOT
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module top (...);
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input clk, rst, d1, d2;
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output q1, q2;
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always @(posedge clk)
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if (clk)
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q1 <= d1;
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always @(posedge clk, posedge rst)
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if (rst)
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q2 <= 0;
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else if (clk)
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q2 <= d2;
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endmodule
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EOT
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proc
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opt
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select -assert-count 1 t:$dff
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select -assert-count 1 w:clk %a %co t:$dff %i
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select -assert-count 1 w:d1 %a %co t:$dff %i
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select -assert-count 1 w:q1 %a %ci t:$dff %i
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select -assert-count 1 t:$adff
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select -assert-count 1 w:clk %a %co t:$adff %i
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select -assert-count 1 w:rst %a %co t:$adff %i
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select -assert-count 1 w:d2 %a %co t:$adff %i
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select -assert-count 1 w:q2 %a %ci t:$adff %i
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