mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
b6e61c16b1
see also previous commit Also updates `scripting_intro.rst` to use literal includes, and uses individual image outputs to avoid the intermediary `.tex` file to join them all.
27 lines
1.4 KiB
TeX
27 lines
1.4 KiB
TeX
\documentclass[12pt,tikz]{standalone}
|
|
\pdfinfoomitdate 1
|
|
\pdfsuppressptexinfo 1
|
|
\pdftrailerid{}
|
|
\usepackage[utf8]{inputenc}
|
|
\usepackage{amsmath}
|
|
\usepackage{pgfplots}
|
|
\usepackage{tikz}
|
|
\pagestyle{empty}
|
|
|
|
\begin{document}
|
|
\begin{tikzpicture}
|
|
\tikzstyle{entity} = [draw, fill=gray!10, rectangle, minimum height=3em, minimum width=7em, node distance=5em, font={\ttfamily}]
|
|
\node[entity] (design) {RTLIL::Design};
|
|
\node[entity] (module) [right of=design, node distance=11em] {RTLIL::Module} edge [-latex] node[above] {\tiny 1 \hskip3em N} (design);
|
|
|
|
\node[entity] (process) [fill=green!10, right of=module, node distance=10em] {RTLIL::Process} (process.west) edge [-latex] (module);
|
|
\node[entity] (memory) [fill=red!10, below of=process] {RTLIL::Memory} edge [-latex] (module);
|
|
\node[entity] (wire) [fill=blue!10, above of=process] {RTLIL::Wire} (wire.west) edge [-latex] (module);
|
|
\node[entity] (cell) [fill=blue!10, above of=wire] {RTLIL::Cell} (cell.west) edge [-latex] (module);
|
|
|
|
\node[entity] (case) [fill=green!10, right of=process, node distance=10em] {RTLIL::CaseRule} edge [latex-latex] (process);
|
|
\node[entity] (sync) [fill=green!10, above of=case] {RTLIL::SyncRule} edge [-latex] (process);
|
|
\node[entity] (switch) [fill=green!10, below of=case] {RTLIL::SwitchRule} edge [-latex] (case);
|
|
\draw[latex-] (switch.east) -- ++(1em,0) |- (case.east);
|
|
\end{tikzpicture}
|
|
\end{document}
|