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https://github.com/YosysHQ/yosys
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4b273a4ae9
Fixes a typo and adds another test case that triggers the fallback behavior as the existing tests all trigger the new optimization.
55 lines
853 B
Verilog
55 lines
853 B
Verilog
module test_1(
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input [7:0] a, b, c,
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input s, x,
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output [7:0] y1, y2
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);
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wire [7:0] t1, t2;
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assign t1 = s ? a*b : 0, t2 = !s ? b*c : 0;
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assign y1 = x ? t2 : t1, y2 = x ? t1 : t2;
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endmodule
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module test_2(
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input s,
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input [7:0] a, b, c,
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output reg [7:0] y
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);
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always @* begin
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y <= 'bx;
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if (s) begin
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if (a * b > 8)
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y <= b / c;
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else
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y <= c / b;
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end else begin
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if (b * c > 8)
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y <= a / b;
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else
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y <= b / a;
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end
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end
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endmodule
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module test_3(
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input [3:0] s,
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input [7:0] a, b, c,
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output reg [7:0] y0,
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output reg [7:0] y1,
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output reg [7:0] y2,
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output reg [7:0] y3,
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);
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wire is_onehot = s & (s - 1);
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always @* begin
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y0 <= 0;
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y1 <= 0;
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y2 <= 0;
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y3 <= 0;
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if (s < 3) y0 <= b / c;
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if (3 <= s && s < 6) y1 <= c / b;
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if (6 <= s && s < 9) y2 <= a / b;
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if (9 <= s && s < 12) y3 <= b / a;
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end
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endmodule
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