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55dc5a4e4f
* xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
29 lines
653 B
Verilog
29 lines
653 B
Verilog
(* abc9_box *)
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module $__ABC9_DELAY (input I, output O);
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parameter DELAY = 0;
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specify
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(I => O) = DELAY;
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endspecify
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endmodule
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module $__ABC9_SCC_BREAKER (input [WIDTH-1:0] I, output [WIDTH-1:0] O);
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parameter WIDTH = 0;
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endmodule
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(* abc9_flop, abc9_box, lib_whitebox *)
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module $__DFF_N__$abc9_flop (input C, D, Q, output n1);
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assign n1 = D;
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specify
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$setup(D, posedge C, 0);
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(posedge C => (n1:D)) = 0;
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endspecify
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endmodule
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(* abc9_flop, abc9_box, lib_whitebox *)
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module $__DFF_P__$abc9_flop (input C, D, Q, output n1);
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assign n1 = D;
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specify
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$setup(D, posedge C, 0);
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(posedge C => (n1:D)) = 0;
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endspecify
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endmodule
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