mirror of
https://github.com/YosysHQ/yosys
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0ec5f1b756
- Techlib pmgens are now in relevant techlibs/*. - `peepopt` pmgens are now in passes/opt. - `test_pmgen` is still in passes/pmgen. - Update `Makefile.inc` and `.gitignore` file(s) to match new `*_pm.h` location, as well as the `#include`s. - Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the top level Makefile. - Update pmgen target to use `$(notdir $*)` (where `$*` is the part of the file name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir $@))`.
59 lines
2 KiB
Text
59 lines
2 KiB
Text
pattern formal_clockgateff
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// Detects the most common clock gating pattern using a latch and replaces it
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// with a functionally equivalent pattern based on a flip-flop. The latch
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// based pattern has a combinational path from the enable input to output after
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// clk2fflogic, but this is a stable loop and the flip-flop based pattern does
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// not exhibit this.
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//
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// This optimization is suitable for formal to prevent false comb loops, but
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// should not be used for synthesis where the latch is an intentional choice
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//
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// Latch style:
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// always @* if (!clk_i) latched_en = en;
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// assign gated_clk_o = latched_en & clk_i;
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//
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// Flip-flop style:
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// always @(posedge clk) flopped_en <= en;
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// assign gated_clk_o = flopped_en & clk_i;
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state <SigSpec> clk en latched_en gated_clk
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state <IdString> latched_en_port_name
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match latch
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select latch->type == $dlatch
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select param(latch, \WIDTH) == 1
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select param(latch, \EN_POLARITY).as_bool() == false
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set clk port(latch, \EN)
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set en port(latch, \D)
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set latched_en port(latch, \Q)
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endmatch
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match and_gate
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select and_gate->type.in($and, $logic_and)
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select param(and_gate, \A_WIDTH) == 1
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select param(and_gate, \B_WIDTH) == 1
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select param(and_gate, \Y_WIDTH) == 1
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choice <IdString> clk_port {\A, \B}
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define <IdString> latch_port {clk_port == \A ? \B : \A}
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index <SigSpec> port(and_gate, clk_port) === clk
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index <SigSpec> port(and_gate, latch_port) === latched_en
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set gated_clk port(and_gate, \Y)
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set latched_en_port_name latch_port
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endmatch
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code
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log("replacing clock gate pattern in %s with ff: latch=%s, and=%s\n",
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log_id(module), log_id(latch), log_id(and_gate));
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// Add a flip-flop and rewire the AND gate to use the output of this flop
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// instead of the latch. We don't delete the latch in case its output is
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// used to drive other nodes. If it isn't, it will be trivially removed by
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// clean
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SigSpec flopped_en = module->addWire(NEW_ID);
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module->addDff(NEW_ID, clk, en, flopped_en, true, latch->get_src_attribute());
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and_gate->setPort(latched_en_port_name, flopped_en);
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did_something = true;
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accept;
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endcode
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