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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
74 lines
2.3 KiB
C++
74 lines
2.3 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct MemoryNordffPass : public Pass {
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MemoryNordffPass() : Pass("memory_nordff", "extract read port FFs from memories") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_nordff [options] [selection]\n");
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log("\n");
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log("This pass extracts FFs from memory read ports. This results in a netlist\n");
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log("similar to what one would get from not calling memory_dff.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing MEMORY_NORDFF pass (extracting $dff cells from memories).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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// if (args[argidx] == "-nordff" || args[argidx] == "-wr_only") {
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// flag_wr_only = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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FfInitVals initvals(&sigmap, module);
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for (auto &mem : Mem::get_selected_memories(module))
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{
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bool changed = false;
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for (int i = 0; i < GetSize(mem.rd_ports); i++) {
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if (mem.rd_ports[i].clk_enable) {
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mem.extract_rdff(i, &initvals);
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changed = true;
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}
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}
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if (changed)
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mem.emit();
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}
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}
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}
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} MemoryNordffPass;
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PRIVATE_NAMESPACE_END
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