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This is @KrystalDelusion's suggestion in PR #5141 to verify sensible implementation of all 4 possible full_case/parallel_case combinations. (Also including two similar tests to check the Verilog frontend applies the correct attributes when given SystemVerilog priority/unique case and if statements.) |
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| .. | ||
| .gitignore | ||
| bug2619.ys | ||
| bug2656.ys | ||
| bug2962.ys | ||
| bug4712.ys | ||
| bug_1268.v | ||
| bug_1268.ys | ||
| case_attr.ys | ||
| clean_undef_case.ys | ||
| proc_dff.ys | ||
| proc_rom.ys | ||
| rmdead.v | ||
| rmdead.ys | ||
| run-test.sh | ||