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22 lines
347 B
Text
22 lines
347 B
Text
log -header "Simple reduce_or annotation"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire [1:0] x
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);
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assign x[0] = |a[2:0];
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assign x[1] = |a;
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endmodule
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EOF
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check -assert
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# Annotate uniqueness coefficients
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annotate_unqcoef
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# Check uniqueness coefficients are correct
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# TODO
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design -reset
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log -pop
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