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17 lines
315 B
Systemverilog
17 lines
315 B
Systemverilog
module functions01;
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wire [3:0]x;
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wire [$size(x)-1:0]x_size;
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wire [$size({x, x})-1:0]xx_size;
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wire [3:0]y[0:5];
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wire [$size(y)-1:0]y_size;
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wire [3:0]z[0:5][0:7];
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wire [$size(z)-1:0]z_size;
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wire [$bits(x)-1:0]x_bits;
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wire [$bits({x, x})-1:0]xx_bits;
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wire [$bits(y)-1:0]y_bits;
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wire [$bits(z)-1:0]z_bits;
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endmodule
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