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yosys/frontends/verilog
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Dag Lem a862642fac Correct interpretation of SystemVerilog C-style array dimensions 
IEEE Std 1800™-2017 7.4.2 specifies that [size] is the same as [0:size-1].
2022-11-13 07:41:25 +01:00
..
.gitignore
const2ast.cc
Makefile.inc
preproc.cc set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
preproc.h verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
verilog_frontend.cc verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_frontend.h verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_lexer.l verilog: support for time scale delay values 2022-02-14 15:58:31 +01:00
verilog_parser.y Correct interpretation of SystemVerilog C-style array dimensions 2022-11-13 07:41:25 +01:00