Dag Lem a862642fac Correct interpretation of SystemVerilog C-style array dimensions ... IEEE Std 1800™-2017 7.4.2 specifies that [size] is the same as [0:size-1].		2022-11-13 07:41:25 +01:00
..
.gitignore	Add "make coverage"	2018-08-27 14:22:21 +02:00
const2ast.cc	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
Makefile.inc	Treat all bison warnings as errors in verilog front-end	2020-07-15 11:57:31 +02:00
preproc.cc	set default_nettype to wire for resetall	2022-08-10 13:28:19 +02:00
preproc.h	verilog: save and restore overwritten macro arguments	2021-07-28 21:52:16 -04:00
verilog_frontend.cc	verilog: Squash a memory leak.	2021-06-14 17:07:41 +02:00
verilog_frontend.h	verilog: Squash a memory leak.	2021-06-14 17:07:41 +02:00
verilog_lexer.l	verilog: support for time scale delay values	2022-02-14 15:58:31 +01:00
verilog_parser.y	Correct interpretation of SystemVerilog C-style array dimensions	2022-11-13 07:41:25 +01:00