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yosys/frontends
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Clifford Wolf 5387ccb041 Set Verific flag vhdl_support_variable_slice=1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-09 21:03:23 +01:00
..
ast
blif
ilang
json
liberty
verific Set Verific flag vhdl_support_variable_slice=1 2018-11-09 21:03:23 +01:00
verilog