mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-02-10 11:01:04 +00:00
Code Activity
yosys/frontends
History
Catherine 1236bb65b6 read_verilog: don't include empty opt_sva_label in span. 
Consider this SystemVerilog file:

    module top(...);
      input clk;
      input [7:0] data;
      input ack;

      always @(posedge clk)
        if (ack) begin
          assert(data != 8'h0a);
        end
    endmodule

Before this commit, the span for the assert was:

        if (ack) begin>
          assert(data != 8'h0a)<;

After this commit, the span for the assert is:

        if (ack) begin
          >assert(data != 8'h0a)<;

This helps editor integrations that only look at the beginning
of the span.
2024-02-08 14:25:35 +00:00
..
aiger
ast Add new $check cell to represent assertions with a message. 2024-02-01 20:10:39 +01:00
blif
json
liberty
rpc
rtlil
verific
verilog read_verilog: don't include empty opt_sva_label in span. 2024-02-08 14:25:35 +00:00