3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-01 11:51:21 +00:00
yosys/tests/liberty/busdef2.lib.verilogsim.ok
2024-10-05 01:33:56 -10:00

4 lines
72 B
Text

module not_cell (Y);
output Y;
assign Y = !A[0]; // !A[0]
endmodule