mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-20 14:20:32 +00:00
7 lines
122 B
Verilog
7 lines
122 B
Verilog
module sdff( input d, clk, rst, output reg q );
|
|
always @( posedge clk)
|
|
if (rst)
|
|
q <= 0;
|
|
else
|
|
q <= d;
|
|
endmodule
|