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2cab4ff173
This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that nowrshmsk is actually tested. Stride is extracted from indexing of two-dimensional packed arrays and variable slices on the form dst[i*stride +: width] = src, and is used to optimize the generated CASE block. Also uses less confusing variable names for indexing of lhs wires.
77 lines
1.8 KiB
Verilog
77 lines
1.8 KiB
Verilog
module gate(
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(* nowrshmsk = `ALT *)
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output reg [`LEFT:`RIGHT] out_u, out_s,
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input wire data,
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input wire [1:0] sel1, sel2
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);
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always @* begin
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out_u = 0;
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out_s = 0;
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case (`SPAN)
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1: begin
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out_u[sel1*sel2] = data;
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out_s[$signed(sel1*sel2)] = data;
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end
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2: begin
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out_u[sel1*sel2+:2] = {data, data};
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out_s[$signed(sel1*sel2)+:2] = {data, data};
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end
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3: begin
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out_u[sel1*sel2+:3] = {data, data, data};
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out_s[$signed(sel1*sel2)+:3] = {data, data, data};
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end
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4: begin
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out_u[sel1*sel2+:4] = {data, data, data, data};
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out_s[$signed(sel1*sel2)+:4] = {data, data, data, data};
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end
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endcase
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end
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endmodule
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module gold(
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output reg [`LEFT:`RIGHT] out_u, out_s,
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input wire data,
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input wire [1:0] sel1, sel2
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);
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task set;
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input integer a, b;
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localparam LOW = `LEFT > `RIGHT ? `RIGHT : `LEFT;
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localparam HIGH = `LEFT > `RIGHT ? `LEFT : `RIGHT;
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if (LOW <= a && a <= HIGH)
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out_u[a] = data;
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if (LOW <= b && b <= HIGH)
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out_s[b] = data;
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endtask
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always @* begin
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out_u = 0;
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out_s = 0;
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case (sel1*sel2)
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2'b00: set(0, 0);
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2'b01: set(1, 1);
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2'b10: set(2, -2);
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2'b11: set(3, -1);
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endcase
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if (`SPAN >= 2)
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case (sel1*sel2)
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2'b00: set(1, 1);
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2'b01: set(2, 2);
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2'b10: set(3, -1);
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2'b11: set(4, 0);
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endcase
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if (`SPAN >= 3)
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case (sel1*sel2)
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2'b00: set(2, 2);
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2'b01: set(3, 3);
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2'b10: set(4, 0);
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2'b11: set(5, 1);
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endcase
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if (`SPAN >= 4)
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case (sel1*sel2)
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2'b00: set(3, 3);
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2'b01: set(4, 4);
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2'b10: set(5, 1);
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2'b11: set(6, 2);
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endcase
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end
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endmodule
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