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yosys/tests
Rupert Swarbrick 044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
..
aiger
arch fix argument order for macOS compatibility 2020-03-18 15:11:49 +01:00
asicworld
bram
errors
fsm
hana
liberty
lut
memfile
memories
opt
opt_share
proc
realmath
rpc
sat
select Do not warn on empty selection with prefixed arg_memb. 2020-03-23 17:50:11 +00:00
share
simple
simple_abc9
smv
sva
svinterfaces
svtypes
techmap techmap: Fix cell names with _TECHMAP_REPLACE_.* 2020-03-23 11:17:07 +01:00
tools
unit
various Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
vloghtb