| .. |
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abc9_map.v
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intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
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2020-07-04 19:45:10 +02:00 |
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abc9_model.v
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intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF
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2020-07-04 19:45:10 +02:00 |
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abc9_unmap.v
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intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
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2020-07-04 19:45:10 +02:00 |
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alm_map.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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alm_sim.v
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intel_alm: Documentation improvements
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2020-04-21 19:38:15 +02:00 |
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arith_alm_map.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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bram_m10k.txt
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synth_intel_alm: alternative synthesis for Intel FPGAs
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2020-04-15 11:40:41 +02:00 |
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bram_m10k_map.v
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intel_alm: direct LUTRAM cell instantiation
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2020-05-07 21:03:13 +02:00 |
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bram_m20k.txt
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synth_intel_alm: alternative synthesis for Intel FPGAs
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2020-04-15 11:40:41 +02:00 |
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bram_m20k_map.v
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synth_intel_alm: alternative synthesis for Intel FPGAs
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2020-04-15 11:40:41 +02:00 |
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dff_map.v
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intel_alm: Documentation improvements
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2020-04-21 19:38:15 +02:00 |
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dff_sim.v
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intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF
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2020-07-04 19:45:10 +02:00 |
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lutram_mlab.txt
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intel_alm: direct LUTRAM cell instantiation
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2020-05-07 21:03:13 +02:00 |
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megafunction_bb.v
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intel_alm: direct LUTRAM cell instantiation
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2020-05-07 21:03:13 +02:00 |
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mem_sim.v
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intel_alm: ABC9 sequential optimisations
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2020-07-04 19:45:10 +02:00 |
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quartus_rename.v
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intel_alm: direct LUTRAM cell instantiation
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2020-05-07 21:03:13 +02:00 |
