Miodrag Milanovic 2bcd55f1ae Export wire properties as well in EDIF		2020-01-10 12:33:58 +01:00
..
aiger	write_xaiger: make more robust, update doc	2020-01-06 10:23:04 -08:00
blif	RTLIL::S{0,1} -> State::S{0,1}	2019-08-07 11:12:38 -07:00
btor	Use cell name for btor bad state props when it is a public name	2019-11-14 11:57:38 +01:00
edif	Export wire properties as well in EDIF	2020-01-10 12:33:58 +01:00
firrtl	Merge pull request #1258 from YosysHQ/eddie/cleanup	2019-08-10 09:52:14 +02:00
ilang	RTLIL::S{0,1} -> State::S{0,1}	2019-08-07 11:12:38 -07:00
intersynth	substr() -> compare()	2019-08-07 12:20:08 -07:00
json	Implement improved JSON attr/param encoding	2019-08-01 12:34:52 +02:00
protobuf	Add aiger and protobuf backends binary support	2019-09-28 09:51:48 +02:00
simplec	Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs	2019-08-06 04:47:55 +02:00
smt2	Bugfix in smtio vcd handling of $-identifiers	2019-10-23 00:04:34 +02:00
smv	substr() -> compare()	2019-08-07 12:20:08 -07:00
spice	Add "whitebox" attribute, add "read_verilog -wb"	2019-04-18 17:45:47 +02:00
table	Add "whitebox" attribute, add "read_verilog -wb"	2019-04-18 17:45:47 +02:00
verilog	write_verilog: add -extmem option, to write split memory init files.	2019-11-18 01:27:21 +00:00