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17 lines
254 B
Verilog
17 lines
254 B
Verilog
module top(out, clk, in);
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output [7:0] out;
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input signed clk, in;
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reg signed [7:0] out;
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`ifndef NO_INIT
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initial begin
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out = 0;
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end
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`endif
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always @(posedge clk)
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begin
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out <= out >> 1;
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out[7] <= in;
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end
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endmodule
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