mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-02-08 01:58:00 +00:00
Code Activity
yosys/backends/verilog
History
whitequark 3c643c57df write_verilog: add -extmem option, to write split memory init files. 
Some toolchains (in particular Quartus) are pathologically slow if
a large amount of assignments in `initial` blocks are used.
2019-11-18 01:27:21 +00:00
..
Makefile.inc
verilog_backend.cc