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yosys/tests/arch/common
Dan Ravensloft 1a07b330f8 intel_alm: Add multiply signedness to cells
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
2020-08-26 22:50:16 +02:00
..
memory_attributes Fixing compiler warning/issues. Moving test script to the correct place 2019-12-16 10:23:45 -06:00
add_sub.v
adffs.v
blockram.v ice40: add support for both 1364.1 and LSE RAM/ROM attributes. 2020-02-06 14:58:20 +00:00
blockrom.v ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. 2020-02-06 16:52:51 +00:00
counter.v
dffs.v
fsm.v
latches.v
logic.v
lutram.v
mul.v intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
mux.v
shifter.v
tribuf.v