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yosys/techlibs/ice40
2019-08-30 10:30:46 -07:00
..
tests
.gitignore
abc_hx.box Rename boxes too 2019-08-29 07:03:32 -07:00
abc_hx.lut
abc_lp.box Rename boxes too 2019-08-29 07:03:32 -07:00
abc_lp.lut
abc_u.box Rename boxes too 2019-08-29 07:03:32 -07:00
abc_u.lut
arith_map.v
brams.txt
brams_init.py
brams_map.v
cells_map.v Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER 2019-08-12 12:19:25 -07:00
cells_sim.v Comment out SB_MAC16 arrival time for now, need to handle all its modes 2019-08-28 19:09:29 -07:00
ice40_braminit.cc
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc Do not overwrite LUT param 2019-08-28 18:46:53 -07:00
latches_map.v
Makefile.inc
synth_ice40.cc LX -> LP 2019-08-28 19:02:54 -07:00