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https://github.com/YosysHQ/yosys
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74 lines
No EOL
2.5 KiB
Text
74 lines
No EOL
2.5 KiB
Text
read_verilog -sv pipe_mul.sv
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design -save pristine
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# 18x18 MULT
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design -load pristine
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hierarchy -top mul18_pipe
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synth_nexus -family lifcl -top mul18_pipe
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select -assert-count 1 t:MULT18X18 r:REGINPUTA=REGISTER r:REGINPUTB=REGISTER r:REGOUTPUT=REGISTER
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select -assert-count 0 t:FD1P3*
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# 18x18 MULT (signed)
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design -load pristine
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hierarchy -top mul18_pipe_signed
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synth_nexus -family lifcl -top mul18_pipe_signed
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select -assert-count 1 t:MULT18X18 r:REGINPUTA=REGISTER r:REGINPUTB=REGISTER r:REGOUTPUT=REGISTER
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select -assert-count 0 t:FD1P3*
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# 18x18 MULT (input only)
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design -load pristine
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hierarchy -top mul18_pipe_in_only
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synth_nexus -family lifcl -top mul18_pipe_in_only
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select -assert-count 1 t:MULT18X18 r:REGINPUTA=REGISTER r:REGINPUTB=REGISTER r:REGOUTPUT=BYPASS
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select -assert-count 0 t:FD1P3*
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# 18x18 MULT (output only)
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design -load pristine
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hierarchy -top mul18_pipe_out_only
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synth_nexus -family lifcl -top mul18_pipe_out_only
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select -assert-count 1 t:MULT18X18 r:REGINPUTA=BYPASS r:REGINPUTB=BYPASS r:REGOUTPUT=REGISTER
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select -assert-count 0 t:FD1P3*
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# 18x18 MULT (reset)
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design -load pristine
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hierarchy -top mul18_pipe_io_rst
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synth_nexus -family lifcl -top mul18_pipe_io_rst
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select -assert-count 1 t:MULT18X18 r:REGINPUTA=REGISTER r:REGINPUTB=REGISTER r:REGOUTPUT=REGISTER
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select -assert-count 0 t:FD1P3*
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# 24x24 MUL -> pipelined 36X36 MULT
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design -load pristine
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hierarchy -top mul24_io
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synth_nexus -family lifcl -top mul24_io
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select -assert-count 1 t:MULT36X36 r:REGINPUTA=REGISTER r:REGINPUTB=REGISTER r:REGOUTPUT=REGISTER
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select -assert-count 0 t:FD1P3*
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# 32x32 MUL -> pipelined 36X36 MULT
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design -load pristine
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hierarchy -top mul32_io
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synth_nexus -family lifcl -top mul32_io
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select -assert-count 1 t:MULT36X36 r:REGINPUTA=REGISTER r:REGINPUTB=REGISTER r:REGOUTPUT=REGISTER
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select -assert-count 0 t:FD1P3*
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# reject
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# DSP reg is rising-edge
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design -load pristine
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hierarchy -top mul18_negedge
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synth_nexus -family lifcl -top mul18_negedge
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select -assert-count 1 t:MULT18X18 r:REGINPUTA=BYPASS r:REGINPUTB=BYPASS r:REGOUTPUT=BYPASS
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select -assert-min 1 t:FD1P3*
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# DSP reg only resets to 0
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design -load pristine
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hierarchy -top mul18_rst_nonzero
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synth_nexus -family lifcl -top mul18_rst_nonzero
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select -assert-count 1 t:MULT18X18 r:REGINPUTA=BYPASS r:REGINPUTB=BYPASS r:REGOUTPUT=BYPASS
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select -assert-min 1 t:FD1P3*
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# two clocks feeding input regs -> can't share one CLK pin
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design -load pristine
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hierarchy -top mul18_two_clock
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synth_nexus -family lifcl -top mul18_two_clock
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select -assert-count 1 t:MULT18X18 r:REGINPUTA=BYPASS r:REGINPUTB=BYPASS
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select -assert-min 1 t:FD1P3* |