Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string		2024-10-14 06:28:12 +02:00
..
aiger	read_aiger: Fix incorrect read of binary Aiger without outputs	2024-04-29 14:06:58 +01:00
arch	wheels: fix missing yosys-abc/share directory	2024-10-09 13:09:14 +03:00
asicworld
bind
blif
bram
cxxrtl	cxxrtl: test stream operator	2024-10-01 13:25:07 +02:00
errors
fmt
fsm
functional	functional tests: run from make tests but not smtlib/rkt tests	2024-09-04 10:30:08 +01:00
hana
liberty	tests: Add trivial liberty -unit_delay test	2024-09-18 16:17:03 +02:00
lut
memfile
memlib	Move parameters to module declaration	2024-04-08 12:44:37 +02:00
memories	Move parameters to module declaration	2024-04-08 12:44:37 +02:00
opt	peepopt: avoid shift-amount underflow	2024-06-13 23:30:07 +02:00
opt_share
proc	proc_dff: add tests	2024-08-28 16:24:47 +01:00
realmath
rpc
sat
select
share
sim
simple	write_verilog: don't assign to a reg.	2024-04-03 13:06:45 +02:00
simple_abc9
smv
sva	tests/sva: Skip sva tests that use SBY until SBY is compatible again	2024-03-05 14:37:33 +01:00
svinterfaces
svtypes
techmap	Adjust operation naming in aigmap test	2024-09-17 13:55:58 +02:00
tools
unit	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
various	Merge pull request #4613 from povik/err-never-silence	2024-10-07 16:12:31 +02:00
verific	Add left and right bound properties to wire. Add test. Fix printing	2024-09-10 12:52:42 +02:00
verilog	Added cast to type support (#4284)	2024-09-29 17:03:01 -04:00
vloghtb
xprop
gen-tests-makefile.sh