mirror of
https://github.com/YosysHQ/yosys
synced 2026-01-27 12:28:44 +00:00
3 lines
83 B
Text
3 lines
83 B
Text
read_verilog bug3670.v
|
|
read_verilog -lib -specify +/analogdevices/cells_sim.v
|
|
abc9
|