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33 lines
709 B
Systemverilog
33 lines
709 B
Systemverilog
`define TEST(kwd) \
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kwd kwd``_1; \
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kwd kwd``_2; \
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initial kwd``_1 = 1; \
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assign kwd``_2 = 1;
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`define TEST_VAR(kwd) \
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var kwd var_``kwd``_1; \
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var kwd var_``kwd``_2; \
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initial var_``kwd``_1 = 1; \
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assign var_``kwd``_2 = 1;
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`define TEST_WIRE(kwd) \
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wire kwd wire_``kwd``_1; \
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wire kwd wire_``kwd``_2; \
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initial wire_``kwd``_1 = 1; \
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assign wire_``kwd``_2 = 1;
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module top;
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`TEST(wire) // wire assigned in a block
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`TEST(reg) // reg assigned in a continuous assignment
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`TEST(logic)
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`TEST(integer)
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`TEST_VAR(reg) // reg assigned in a continuous assignment
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`TEST_VAR(logic)
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`TEST_VAR(integer)
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`TEST_WIRE(logic) // wire assigned in a block
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`TEST_WIRE(integer) // wire assigned in a block
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endmodule
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