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77 lines
2.2 KiB
Systemverilog
77 lines
2.2 KiB
Systemverilog
`default_nettype none
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module evil;
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parameter HI = 3;
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parameter LO = 0;
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parameter SPAN = 1;
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parameter [HI:LO] A_VAL = 4'b0110;
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parameter [HI:LO] B_VAL = 4'b1100;
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parameter [2:0] SWAPS = 0;
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localparam D_LEFT = !(SWAPS[0]) ? HI : LO;
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localparam D_RIGHT = (SWAPS[0]) ? HI : LO;
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localparam E_LEFT = !(SWAPS[1]) ? HI : LO;
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localparam E_RIGHT = (SWAPS[1]) ? HI : LO;
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localparam F_LEFT = !(SWAPS[2]) ? HI : LO;
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localparam F_RIGHT = (SWAPS[2]) ? HI : LO;
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localparam [HI:LO] A_CONST = A_VAL;
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localparam [HI:LO] B_CONST = B_VAL;
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localparam [HI:LO] C_CONST = F(A_CONST, B_CONST);
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reg [HI:LO] C_WIRE, C_FUNC;
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always @* begin
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assert (C_CONST == C_WIRE);
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assert (C_CONST == C_FUNC);
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end
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initial begin : blk
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reg [HI:LO] A_WIRE;
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reg [HI:LO] B_WIRE;
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reg [D_LEFT:D_RIGHT] D;
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reg [E_LEFT:E_RIGHT] E;
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reg [F_LEFT:F_RIGHT] F_WIRE;
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reg [31:0] i;
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A_WIRE = A_VAL;
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B_WIRE = B_VAL;
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D = A_WIRE;
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E = B_WIRE;
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F_WIRE = 0;
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for (i = LO; i + SPAN < HI; i = i + SPAN)
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if (SPAN == 1)
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F_WIRE[i] = D[i] && E[i];
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else
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F_WIRE[i+:SPAN] = D[i+:SPAN] && E[i+:SPAN];
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C_WIRE = F_WIRE;
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C_FUNC = F(A_WIRE, B_WIRE);
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end
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function automatic [F_LEFT:F_RIGHT] F(
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input [D_LEFT:D_RIGHT] D,
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input [E_LEFT:E_RIGHT] E);
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reg [31:0] i;
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F = 0;
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for (i = LO; i + SPAN < HI; i = i + SPAN)
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if (SPAN == 1)
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F[i] = D[i] && E[i];
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else
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F[i+:SPAN] = D[i+:SPAN] && E[i+:SPAN];
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endfunction
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endmodule
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module top;
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for (genvar hi = 0; hi < 3; hi++)
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for (genvar lo = 0; lo <= hi; lo++)
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for (genvar span = 1; span <= hi - lo + 1; span++)
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for (genvar a_val = 0; a_val < 2 ** (hi - lo + 1); a_val++)
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for (genvar b_val = 0; b_val < 2 ** (hi - lo + 1); b_val++)
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for (genvar swaps = 0; swaps < 2 ** 3; swaps++)
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evil #(
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.HI(hi),
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.LO(lo),
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.SPAN(span),
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.A_VAL(a_val),
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.B_VAL(b_val),
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.SWAPS(swaps)
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) e();
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endmodule
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