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https://github.com/YosysHQ/yosys
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62 lines
1 KiB
Text
62 lines
1 KiB
Text
# https://github.com/YosysHQ/yosys/issues/1381
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read_verilog <<EOT
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module sub(input i, output o, (* techmap_autopurge *) input j);
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foobar f(i, o, j);
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endmodule
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EOT
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design -stash techmap
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read_verilog <<EOT
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(* blackbox *)
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module sub(input i, output o, input j);
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endmodule
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(* blackbox *)
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module foobar(input i, output o, input j);
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endmodule
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module top(input i, output o);
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sub s0(i, o);
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endmodule
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EOT
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techmap -map %techmap
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hierarchy
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check -assert
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# https://github.com/YosysHQ/yosys/issues/1391
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design -reset
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read_verilog <<EOT
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module sub(input i, output o, (* techmap_autopurge *) input [1:0] j);
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foobar f(i, o, j);
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endmodule
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EOT
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design -stash techmap
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read_verilog <<EOT
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(* blackbox *)
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module sub(input i, output o, input j);
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endmodule
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(* blackbox *)
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module foobar(input i, output o, input j);
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endmodule
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module top(input i, output o);
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sub s0(i, o);
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endmodule
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EOT
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techmap -map %techmap
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hierarchy
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check -assert
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read_verilog -overwrite <<EOT
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module top(input i, output o);
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wire j;
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sub s0(i, o, j);
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endmodule
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EOT
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techmap -map %techmap
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hierarchy
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