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25 lines
694 B
Verilog
25 lines
694 B
Verilog
`default_nettype none
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module hierdefparam_top(input wire [7:0] A, output wire [7:0] Y);
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generate begin:foo
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hierdefparam_a mod_a(.A(A), .Y(Y));
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end endgenerate
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defparam foo.mod_a.bar[0].mod_b.addvalue = 42;
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defparam foo.mod_a.bar[1].mod_b.addvalue = 43;
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endmodule
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module hierdefparam_a(input wire [7:0] A, output wire [7:0] Y);
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genvar i;
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generate
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for (i = 0; i < 2; i=i+1) begin:bar
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wire [7:0] a, y;
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hierdefparam_b mod_b(.A(a), .Y(y));
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end
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endgenerate
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assign bar[0].a = A, bar[1].a = bar[0].y, Y = bar[1].y;
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endmodule
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module hierdefparam_b(input wire [7:0] A, output wire [7:0] Y);
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parameter [7:0] addvalue = 44;
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assign Y = A + addvalue;
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endmodule
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