3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-26 18:48:51 +00:00
yosys/tests
Zachary Snow aa35f24290 sv: auto add nosync to certain always_comb local vars
If a local variable is always assigned before it is used, then adding
nosync prevents latches from being needlessly generated.
2022-01-07 22:53:22 -07:00
..
aiger
arch Fix the tests we just broke 2021-12-10 00:22:37 +01:00
asicworld
bind Add support for parsing the SystemVerilog 'bind' construct 2021-07-16 09:31:39 -04:00
blif
bram Fix the tests we just broke 2021-12-10 00:22:37 +01:00
errors
fsm
hana
liberty
lut
memfile
memories Fix the tests we just broke 2021-12-10 00:22:37 +01:00
opt memory_share: Fix SAT-based sharing for wide ports. 2021-12-20 18:40:14 +01:00
opt_share
proc proc_prune: Make assign removal and promotion per-bit, remember promoted bits. 2021-08-14 15:26:11 +02:00
realmath
rpc
sat
select
share
simple fix iverilog compatibility for new case expr tests 2022-01-03 12:11:41 -07:00
simple_abc9
smv
sva
svinterfaces
svtypes sv: improve support for wire and var with user-defined types 2021-08-12 22:41:41 -06:00
techmap Fix the tests we just broke 2021-12-10 00:22:37 +01:00
tools Fixes in vcdcd.pl for newer Perl versions 2021-10-19 10:56:43 +02:00
unit
various logger: fix unmatched expected warnings and errors 2022-01-04 13:39:34 -07:00
verilog sv: auto add nosync to certain always_comb local vars 2022-01-07 22:53:22 -07:00
vloghtb
gen-tests-makefile.sh