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22 lines
517 B
Text
22 lines
517 B
Text
read_verilog <<EOF
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module top(a, b, y);
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parameter awidth = 6;
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parameter bwidth = 8;
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parameter ywidth = 14;
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input [awidth-1:0] a;
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input [bwidth-1:0] b;
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output [ywidth-1:0] y;
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wire [ywidth-1:0] aext = {{(ywidth-awidth){a[awidth-1]}}, a};
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wire [ywidth-1:0] bext = {{(ywidth-bwidth){b[bwidth-1]}}, b};
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assign y = aext*bext;
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endmodule
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EOF
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opt_clean
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wreduce
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select -assert-count 1 t:$mul
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select -assert-count 1 t:$mul r:A_SIGNED=1 r:B_SIGNED=1 %i %i
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select -assert-count 1 t:$mul r:A_WIDTH=6 r:B_WIDTH=8 %i %i
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